The present invention relates to a method of manufacturing a semiconductor device, and more particularly, it relates to a method of manufacturing a semiconductor device in which the resistance of a gate electrode is decreased by forming a metal silicide layer on a polysilicon film to be used as the gate electrode.
In a manufacturing process for a semiconductor device, in particular, a VLSI, for the purpose of realizing a fine structure, a high packing density, a high operation speed and small power consumption, it is necessary to decrease the resistances of a gate electrode and a source/drain diffusion layer, a parasitic resistance and a parasitic capacitance.
As a measure for decreasing the resistances of a gate electrode and a source/drain diffusion layer, a silicide process for forming a silicide layer, that is, a compound of silicon and a metal, on the gate electrode and the source/drain diffusion layer is known.
Furthermore, in particularly a self aligned silicide (salicide) process, which is a kind of the silicide process, a metal silicide layer is simultaneously formed on a polysilicon film to be used as the gate electrode and on an impurity diffusion layer to be used as the source/drain region. Since the metal silicide layer can be formed on the polysilicon film to be used as the gate electrode and the impurity diffusion layer to be used as the source/drain region in one and the same step in this salicide process, the number of steps and a manufacturing cost can be both decreased. Owing to this advantage, the salicide process is regarded as a promising process required for the refinement of a semiconductor device, and is now variously studied.
However, in a TiSi.sub.2 salicide process and a CoSi.sub.2 salicide process, which are recently particularly in the spotlight among various kinds of the salicide process, a sheet resistance value is characteristically increased in accordance with the refinement in a line width of a gate electrode and a source/drain electrode. The increase of the sheet resistance value caused by the reduction of the line width is a significant problem, and therefore, there is a demand for a technique to suppress the increase of the sheet resistance value while reducing the line width.
As a method of suppressing the increase of a sheet resistance value derived from the reduction of a line width, Japanese Laid-Open Patent Publication Nos. 3-209834 and 5-291180 disclose a pre-amorphous process. In the pre-amorphous process, before depositing a metal film of Ti or Co on a polysilicon film to be used as a gate electrode and an impurity diffusion layer to be used as a source/drain region, the surfaces of the polysilicon film and the impurity diffusion layer are changed into amorphous by implanting impurity ions of As or the like into the polysilicon film and the impurity diffusion layer. As the impurity ion used in the pre-amorphous process, an ion of a comparatively heavy element with a small implantation depth, such as an As ion, is used, and the ion implantation for implanting the As ions is performed in the pre-amorphous process at a dose of approximately 3.times.10.sup.14 /cm.sup.-2.
In adopting the pre-amorphous process in which amorphous layers are respectively formed on the polysilicon film and the impurity diffusion layer before depositing the metal film of Ti or Co, the problem occurring in the salicide process, namely, the increase of a sheet resistance value derived from the reduction of a line width can be suppressed. In the case where the pre-amorphous process is not adopted, the sheet resistance value is vigorously increased generally when the line width is smaller than approximately 0.5 .mu.m. In contrast, in adopting the pre-amorphous process, the sheet resistance value is not largely increased when the line width is decreased to approximately 0.3 .mu.m.
When an implantation energy for the As ions is smaller than 15 KeV, an amorphous layer cannot be definitely formed on the polysilicon film to be used as the gate electrode and the impurity diffusion layer to be used as the source/drain region, and therefore, a metal silicide layer cannot be definitely formed. As a result, a line resistance of the gate electrode and the source/drain electrode cannot be decreased. Accordingly, in the salicide process, it is necessary to implant the impurity ions at the implantation energy of 20 KeV or more so as to form the amorphous layers on the polysilicon film and the impurity diffusion layer.
Now, a conventional method of manufacturing a semiconductor device including the salicide process will be described with reference to FIGS. 20(a) through 20(f).
First, as is shown in FIG. 20(a), on a semiconductor substrate 10 of silicon, an isolation region 11, a gate insulating film 12, a polysilicon film 13 to be used as a gate electrode, a low concentration impurity layer 14, a sidewall 15 and a high concentration impurity layer 16 to be used as a source/drain region are successively formed. Then, the high concentration impurity layer 16 is activated through a heat treatment. The resistance of the polysilicon film 13 is decreased by doping the film with impurity ions. The low concentration impurity layer 14 is an LDD diffusion layer formed for improving the initial characteristic and the reliability of a MOS transistor. Impurity ions are implanted into the high concentration impurity layer 16 by using the polysilicon film 13 and the sidewall 15 as masks.
Next, in order to decrease the sheet resistance of the gate electrode and the source/drain electrode as described above, As ions or the like are implanted into the surfaces of the polysilicon film 13 and the high concentration impurity layer 16, thereby forming an amorphous layer 17 as is shown in FIG. 20(b). Then, the surface of the substrate is cleaned with a hydrofluoride solution. Thereafter, a Ti film 18 with a thickness of, for example, approximately 40 nm is deposited on the entire surface of the semiconductor substrate 10 as is shown in FIG. 20(c).
Then, first annealing is conducted by the rapid thermal annealing (RTA) at a temperature of approximately 650.degree. C. in an atmosphere of nitrogen, so as to cause a reaction between the amorphous layer 17 and the Ti film 18. Thus, a TiSi.sub.2 (C49) film 19 having a crystalline structure designated as C49 is formed on the polysilicon film 13 and the high concentration impurity layer 16 as is shown in FIG. 20(d). In this case, since the first annealing is conducted at a temperature of approximately 650.degree. C., the TiSi.sub.2 (C49) film 19 is formed as a phase having a high resistance of approximately 10 through 20 .OMEGA./.quadrature. (that is, a phase of the C49 structure). Furthermore, since a portion of the Ti film 18 above the isolation region 11 and the sidewall 15 is not in contact with the silicon layer, the silicidation is not proceeded in such a portion, and hence, the Ti film 18 in such a portion becomes a TiN film or remains as an unreacted Ti film.
Next, as is shown in FIG. 20(e), the Ti film 18 above the isolation region 11 and the sidewall 15 is selectively removed by using an etching solution such as sulfuric acid--hydrogen peroxide and ammonia--hydrogen peroxide. Then, second annealing is performed for a short period of time by the RTA at a temperature of approximately 800.degree. C. through 850.degree. C. in an atmosphere of nitrogen. Thus, as is shown in FIG. 20(f), the TiSi.sub.2 (C49) film 19 is changed into a low-resistance TiSi.sub.2 (C54) film 20 having a crystalline structure designated as C54.
Subsequently, although not shown in the drawings, an interlevel insulating film is deposited on the entire surface of the semiconductor substrate 10, and the interlevel insulating film is planarized. Then, a contact hole is formed in the planarized interlevel insulating film and a metal line is formed. In this manner, a conventional semiconductor device is manufactured.
The aforementioned conventional method of manufacturing a semiconductor device has, however, the following problem: In order to suppress the disadvantage peculiar to the salicide process, namely, the increase of a sheet resistance derived from the reduction of a line width, the amorphous layer 17 is formed on the polysilicon film 13 to be used as the gate electrode through the impurity ion implantation. However, depending upon a grain state of silicon crystal of the polysilicon film 13, a phenomenon in which an implanted As ion passes through the grain of the silicon crystal of the polysilicon film 13 as is shown in FIG. 21 (that is, a channeling phenomenon) can be caused. When the silicon crystal of the polysilicon film 13 has a large grain diameter, the degree of the occurrence of the channeling phenomenon is increased, and when the implantation energy for the As ions is large, the degree of the occurrence of the channeling phenomenon is also increased.
FIG. 22 shows a transistor characteristic (Vg-Id characteristic) attained when the amorphous layer 17 is formed by implanting the As ions into the polysilicon film 13 having the grain state as is shown in FIG. 21 with the implantation energy varied. As described above, when the As ions are implanted at the implantation energy smaller than 20 KeV, the resistance of the gate electrode cannot be decreased. When the As ions are implanted at the implantation energy exceeding 20 KeV, the channeling phenomenon can occur in the gate electrode at the rate of one to several thousand or several ten thousand. Accordingly, as is shown in FIG. 22, an off-current flowing through a parallel connection of several ten thousand transistors is increased and the off-current value is fluctuated. When the off-current is increased, the power consumption of the entire VLSI is disadvantageously increased, and when the off-current value is fluctuated, the transistor characteristic is disadvantageously dispersed.
FIG. 23 shows a Vg-S parameter (swing) characteristic attained by a parallel connection of several ten thousand MOS transistors each manufactured by implanting the As ions at a dose of 3.times.10.sup.14 cm.sup.-2 with the implantation energy varied. In other words, the graph of FIG. 23 is obtained by plotting the inclination of the Vg-Id characteristic shown in FIG. 22 at every gate voltage Vg. As is obvious from FIG. 23, when the As ions are implanted at the energy of 20 KeV or more, the channeling phenomenon is caused, resulting in increasing the swing value. In a practical range of the gate voltage Vg, namely, in a region of the gate voltage Vg of 0.4 V or less, when the swing value largely exceeds 80, a leakage current is increased. In FIGS. 22 and 23, a region circled with a dashed line corresponds to a region where the characteristic of the MOS transistor is degraded due to the channeling phenomenon so as to cause a problem in the device performance.
FIG. 24 shows the Vg-Id characteristic of a MOS transistor attained in the case where the channeling phenomenon occurs (shown with a solid line) and in an ideal case (shown with a broken line). When the channeling phenomenon occurs, the Vg-Id characteristic of one MOS transistor is obtained by synthesizing a Vg-Id characteristic of a transistor component Tr1 in a region where the channeling phenomenon does not occur and a Vg-Id characteristic of a transistor component Tr2 in a region where the channeling phenomenon occurs. Therefore, as is shown with the solid line in FIG. 24, a kink phenomenon occurs in the Vg-Id characteristic. When the kink phenomenon occurs in the Vg-Id characteristic, the leakage current is unavoidably increased.